A wiring substrate known in the art includes wiring layers that are formed on upper and lower surfaces of an insulation layer and via wirings that connect the upper and lower wiring layers to each other. In such a wiring substrate, copper foils are adhered to the upper and lower surfaces of the insulation layer. After forming a through hole in the insulation layer adhered with the copper foils, a seed layer is formed on each copper foil and the wall of the through hole. Then, electrolytic copper plating is performed using the seed layer as a power feeding electrode to form via wirings with the copper plating film formed on the surfaces of the seed layer. Subsequently, etching is performed to pattern each copper foil. This completes the wiring substrate. Japanese Laid-Open Patent Publication No. 2006-278774 discloses such a conventional wiring substrate.